MES202TC  Digital VLSI System Design and Design Automation
Coursework 2 (50%)
Deadline: 21st April 2024
Section A (70 marks)
In this section, you are supposed to design different circuits according to the requirements. You will need to submit your answers with circuit graphs, as well as the basic theory and your analysis.
Problem 1: Implement the equation
(5 marks, inclass exam)
Problem 2: Please design circuits according to the logic expression below,
1) Design the circuit based on an address decoder, a NOR ROM and a 4 to1 MUX.
(16 marks, inclass exam)
a. Create a table to demonstrate how the operations are performed based on inputs of the MUX and operation code K1K0. (4 marks)
b. Design the gate circuit of the address decoder. (2 marks)
c. Analyze and design the NOR ROM. (6 marks)
d. Connect the ROM, the decoder and MUX. (4 marks)
2) Design the circuit based on a halfadder. (14 marks)
a. Analyze how the inputs of the halfadder are connected to A and B. You can use a table to describe K_{1}, K_{0}, the inputs and the output Z. (6 marks)
b. Derive the input functions. (4 marks)
c. Implement the design of inputs with transistorlevel circuits. (4 marks)
Problem 2: Please design 1 bit ALU with 8 functions as shown in table below, and the ALU are supposed to be based on a fulladder.
Function

Output F

Increment A by 1

F = A + 1

Addition of A and B

F = A + B

Subtract B from A

F = A − B

Decrement A by 1

F = A − 1

OR function

F = A + B

XOR function


XNOR function


Inverter function


1) Circuit design of arithmetic operations. (15 marks)
a. For every arithmetic operation, analyze the connections between inputs and signals A, B. (8 marks)
b. Define an operation code to control the arithmetic operation. (4 marks)
c. Create a table to show how arithmetic operations are performed based on inputs and operation code. (3 marks)
2) Circuit design of logic operation. (20 marks)
a. Based on the design of arithmetic operations, for every logic operation, analyze the connections between inputs and signals A, B. Please provide a definition for an additional operation code if needed. (8 marks)
b. Create a table to show how arithmetic and logic operations are performed based on inputs and operation code. Derive the input functions of the full adder. (6 marks)
c. Implement the input functions with transistorlevel circuits. (6 marks)
Section B (30 marks)
In this section, you are supposed to design a traffic light control system with Verilog hardware description language (HDL). You will need to submit your FSM design, Verilog code, as well as the simulation waveforms. (The Quartus project file is also required to be submitted via Learning Mall Online to the correct drop box.)
Problem: The diagram below shows a traffic intersection, with a main road and a branch road.
Please design a traffic light to meet following requirements:
The traffic light on the main road is green for 28 s, yellow for 3 s and red for 18 s;
Traffic light on the branch road green light lasts 15 s, yellow light lasts 3 seconds, red light 31 seconds.
a. Analyze all the states of the traffic light system, use state machine to describe your design (8 marks).
b. Describe the design in Verilog, explain each part of your design (12 marks).
c. Simulate timing waveforms (10 marks).
d. Test your design with FPGA. If the design did not operate as expected then indicate possible reasons. (optional, if you finish it, you will receive an extra 10 marks in this coursework.)