School of Electrical Engineering and Telecommunications
Term 1, 2024
Assignment 2
ELEC 2141
Digital Circuit Design
Your design for each question should aim at achieving optimized implementation. It should include your design procedure, choice of technology implementation, and simulation results. The gate input cost must be also calculated. Use Xilinx ISE to simulate and verify your design.
Any output of generative AI software used within your assignment must be attributed with full referencing. If the outputs of generative AI such as ChatGPT form part of your submission and is not appropriately attributed, it will be regarded as serious academic misconduct and subject to the standard penalties, which may include 00FL, suspension and exclusion.
*To cite: OpenAI (Year Accessed). ChatGPT. OpenAI.https://openai.com/models/chatgpt/
*Please note that the outputs from these tools are not always accurate, appropriate, nor properly referenced. You should ensure that you have moderated and critically evaluated the outputs from generative AI tools such as ChatGPT before submission.
DUE DATE: April 22, 2024, 23:55
Mr Keggs’ Brewery Security
Mr Keggs is back again. He was so impressed with your efforts in assignment 1 that he has a second task for you! Mr Keggs likes to keep his brewery secure at night, as he is fearful of burglars breaking in and stealing his precious beer.
Figure 1: Mr Keggs’ worst nightmare
Further, he doesn’t trust any of the lock companies. He wants you to design a keypad lock for his brewery. Mr Keggs would like a 4-digit access code - 2337. The keypad is designed as below, with numbers 0-9 and ENTER (E) and CLEAR (C) buttons. To unlock the door, the right sequence of buttons must be pressed, followed by the ENTER button. Pressing the CLEAR button will reset the entered sequence. Now, Mr Keggs realises that one could just use trial and error to unlock the door, and so if an incorrect code is entered 3 times in a row, an alarm must sound (until a reset is applied).
Figure 2: Lock keypad pinout
The lock should take input from a keypad (K[11:0] in the diagram above) and should produce two outputs lock and alarm. If the correct sequence is entered, lock should be LOW for 3 clock cycles, to allow the user to enter the brewery. Additionally, there should be reset and clk inputs. You can assume that the keypad is only pressed whilst the clock is high, and is always released when the clock is low, and furthermore that neither of these events will occur on an edge of the clock (i.e. your input is stable around the clock edges).
For your assignment, you need to
1. Identify the system inputs and outputs.
2. Draw a state diagram for the FSM.
3. Determine if the number of states can be reduced and assign them with binary codes.
4. Design and implement the FSM using D, T and JK flip-flops.
5. Write Verilog HDL models for:
a. The machine based on the state diagram in (2) (behavioural modelling)
b. The JK flip-flop sequential circuit that you implement in (4) (structural or dataflow modelling)
6. Verify the HDL models in (5).
Submission
You must submit your assignment solution as a single pdf on Moodle. This should contain:
. Completed and signed assignment submission form as the front page
. State diagram
. Implementation
. Verilog HDL code (screenshots or text)
. Verilog testbenches (screenshots or text)
. ISim simulation results (screenshots)
Refer to the marking guidelines for further information.
In addition to the report you must also submit all your Verilog modules (excluding testbenches) as separate files. As we will be running an autotest script on your code, you will need to use the following structure:
Behavioural Model: Your top-level module must be named ass2_behavioural and must have the following port names (If these do not exactly match then your design will fail the autotests, order doesn’t matter):
Inputs: clk, reset, keypad[11:0]
Outputs: lock, alarm
Structural/Dataflow Model: Your top-level module must be named ass2_structural and must have the following port names (If these do not exactly match then your design will fail the autotests, order doesn’t matter):
Inputs: clk, reset, keypad[11:0]
Outputs: lock, alarm
Any file that is not a top-level module can be named whatever you like.